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uart
- fpga内嵌入双向串行通讯口 传输波特率可变 可通过查询方式确定发送接收状态 内置256字节发送接收缓冲区 -serial communication
UARTcode
- 串口UART通用异步接收/发送器的VHDL 源代码-Serial UART code
uart
- i like verilog VHDL and system Verilog
uart16450
- uart 16450合集,xilin altera lattice-collection of uart controller 16450
87361001Uart2
- VHDL语言编写的UART串口通讯,2400Hz的波特率时钟-VHDL language UART serial communication, 2400Hz clock of baud rate
cp_uart_6
- 用CPLD驱动UART转USB芯片CP2102的verilog代码，与PC通信 包括CP2102的配置 驱动等-Using CPLD to drive the USB-UART CP2102 interface. verilog code, then communicate with PC, including the configuration and drivers, etc.
s7enable_send0x55_UART_9600
- 最简单的UART发送程序，vhdl编写，系统时钟40M，波特率9600，外Load有效（一个高脉冲）即向PC发送一个字节0X-UART to send the simplest procedures, vhdl prepared, the system clock 40M, baud rate 9600, outside the Load effective (a high-pulse) to the PC sends a byte 0X55
UART2_vhdl
- 这是VHDL语言的uart串口驱动 感觉很难写的 但是这个可以移植的 比较好-This is the VHDL language serial uart driver feel it is very difficult but this can be written by transplantation is better huh
uart_Transmitter
- 自己写的一个uart驱动代码，是一个工程文件，适合初学者，里面的状态机的写法十分值得学习-To write a uart driver code, is a project file, suitable for beginners, which the wording of the state machine is worth learning
URAT_VHDL
- URAT VHDL程序与仿真，包括顶层程序与仿真，波特率发生器VHDL程序， UART发送器程序与仿真，UART接收器程序与仿真-URAT VHDL procedures and simulation, including the top-level procedures and simulation, VHDL program baud rate generator, UART transmitter and simulation program, UART receiver and simu
xapp345_verilog
- IrDA & UART Design (Verilog)
uart
- this a verilog code about serial transmit receive.-this is a verilog code about serial transmit receive.
uart_test_ok_921
- 一个简单的uart 源码，接收一个字符并发回，通过测试，可以使用的，输入时钟12mhz,发送速率96-A simple uart source code, receiving a character and send back through the test, can be used, input clock 12mhz, sending rate 9600
uart
- 用VHDL编写的RS232串口的通信程序-Written with the VHDL serial RS232 communication program
uart_0910
- uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of fr
URAT_VHDL_CODE
- altera公司的fpga源代码，用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.
fpga
- fpga数字电子系统设计与开发 ISE I2C UART usb vga -ISE I2C UART usb vga
lab4
- vhdl uart lab ENTITY uart IS PORT ( SIGNAL clock,reset : IN STD_LOGIC SIGNAL sdatain : IN STD_LOGIC SIGNAL oready, sdataout : INOUT STD_LOGIC SIGNAL iready : INOUT STD_LOGIC SIGNAL charin : INOUT STD_L
UARTipcore
- 这是一个关于UART的IP核，用VHDL写的。经过本人的鉴证，非常实用并且写的非常好。-This is one of the IP core on the UART, using VHDL written. After my verification, very practical and very well written.
vhdl
- VHDL语言的UART串行接口芯片设计程序清单 附录1 数据接收据器的VHDL语言描述清单-vhdl serial